A new version of the EGG system can generate the optimal bit-serial multipliers of 8-bit coefficients with a 100% success rate in 15 minutes on an average. The potential of the proposed approach is examined through experimental synthesis of bitserial constant-coefficient multipliers. DISTRIBUTED ARITHMETIC Distributed arithmetic is an efficient procedure for computing inner prod-ucts between a fixed and a variable data vector. A new version of the EGG system can generate the optimal bit-serial multipliers of 8-bit coefficients with a 100% success rate in 15 minutes on an average.ĪB - This paper presents an efficient graph-based evolutionary optimization technique called Evolutionary Graph Generation (EGG), and its application to the design of bit-serial arithmetic circuits, which frequently appear in real-time DSP architectures. The potential of the proposed approach is examined through experimental synthesis of bitserial constant-coefficient multipliers. N2 - This paper presents an efficient graph-based evolutionary optimization technique called Evolutionary Graph Generation (EGG), and its application to the design of bit-serial arithmetic circuits, which frequently appear in real-time DSP architectures. A separate serial port is provided for each DAC. In digital logic applications, bit-serial architectures send data one bit at a time, along a single wire, in contrast to bit-parallel word architectures. High Speed Serial Interface The AD7242/AD7244 provides a high speed, easy-to-use, serial interface allowing direct interfacing to DSP processors and microcontrollers. T1 - Evolutionary graph generation system and its application to bit-serial arithmetic circuit synthesis The part features an on-chip reference, output buffer amplifiers and two 12-bit/14-bit D/A converters.
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